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Five million babies expected to be born in Pakistan in 9 months since Covid-19 outbreak: Unicef
An estimated 29 million babies will be born in South Asia in the nine months after the Covid-19 outbreak was classified as a pandemic by the World Health Organisation (WHO), while five million births will be reported in Pakistan, according to a report released by the United Nations Children's Fund (Unicef).
The report — released on May 6 — has predicted that an estimated 116 million babies will be born across the world in the 40-week period between March 11 and December 16, with almost a quarter of them in South Asia.
India is expected to report 20 million births, the highest in the region, during this period, the report said, followed by Pakistan, Bangladesh (2.4 million) and Afghanistan (one million).
The report also warned that lockdown measures imposed to curb the spread of the coronavirus may cause disruptions in life-saving health services "putting millions of pregnant mothers and their babies at great risk".
"The continuing rapid spread of Covid-19 across South Asia means new mothers and newborns will be greeted by harsh realities, including global containment measures such as lockdowns and curfews, health centres overwhelmed with response efforts, supply and equipment shortages, and a lack of sufficient skilled birth attendants as health workers [...] are redeployed to treat Covid-19 patients.
"Unicef cautions that although evidence suggests that pregnant mothers are not more affected by Covid-19 than others, countries need to ensure they still have access to antenatal, delivery and post-natal services.
"Likewise, sick newborns need emergency services as they are at high risk of death. New families require care to ensure the health and well-being of mothers, support to start breastfeeding, and to get medicines, vaccines and nutrition to keep their babies healthy," the report said.
The UN body urged governments and healthcare providers to take a few steps to save lives in the coming months by:
- Helping women receive regular checkups during their pregnancy, skilled delivery care and post-delivery care
- Ensuring health workers are provided with the necessary personal protective equipment and priority testing and vaccination for Covid-19 when it becomes available
- Ensuring that all infection prevention and control measures are being followed at health facilities
- Allowing healthcare workers to reach pregnant women through home visits, encouraging women living in rural areas to visit maternal waiting homes, and using mobile health strategies for tele-consultations
- Training, protecting and equipping health workers with kits to attend to home births
- Allocating resources to lifesaving services and supplies for maternal and child health
The report also urged pregnant women to take precautionary measures by practicing social distancing, avoiding physical gatherings and using online health services.
Read: Mothers may pass coronavirus to unborn children, say Chinese doctors
It also advised them to continue breastfeeding their children even if they are infected as "the virus has not been found in samples of breast milk".
"Mothers with Covid-19 should wear a mask when feeding their baby, wash hands before and after touching the baby, and routinely clean and disinfect surfaces," it cautioned.
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Five Reasons I'm Excited About Mixed-Signal Verification in 2015
Key Findings: Many more design teams will be reaching the mixed-signal methodology tipping point in 2015. That means you need to have a (verification) plan, and measure and execute against it.
As 2014 draws to a close, it is time to look ahead to the coming years and make a plan. While the macro view of the chip design world shows that is has been a mixed-signal world for a long time, it is has been primarily the digital teams that have rapidly evolved design and verification practices over the past decade. Well, I claim that is about to change. 2015 will be a watershed year for many more design teams because of the following factors:
- 85% of designs are mixed signal, and it is going to stay that way (there is no turning back)
- Advanced node drives new techniques, but they will be applied on all nodes
- Equilibrium of mixed-signal designs being challenged, complexity raises risk level
- Tipping point signs are evident and pervasive, things are going to change
- The convergence of “big A” and “big D” demands true mixed-signal practices
Reason 1: Mixed-signal is dominant
To begin the examination of what is going to change and why, let’s start with what is not changing. IBS reports that mixed signal accounts for over 85% of chip design starts in 2014, and that percentage will rise, and hold steady at 85% in the coming years. It is a mixed-signal world and there is no turning back!
Figure 1. IBS: Mixed-signal design starts as percent of total
The foundational nature of mixed-signal designs in the semiconductor industry is well established. The reason it is exciting is that a stable foundation provides a platform for driving change. (It’s hard to drive on crumbling infrastructure. If you’re from California, you know what I mean, between the potholes on the highways and the earthquakes and everything.)
Reason 2: Innovation in many directions, mostly mixed-signal applications
While the challenges being felt at the advanced nodes, such as double patterning and adoption of FinFET devices, have slowed some from following onto to nodes past 28nm, innovation has just turned in different directions. Applications for Internet of Things, automotive, and medical all have strong mixed-signal elements in their semiconductor content value proposition. What is critical to recognize is that many of the design techniques that were initially driven by advanced-node programs have merit across the spectrum of active semiconductor process technologies. For example, digitally controlled, calibrated, and compensated analog IP, along with power-reducing mutli-supply domains, power shut-off, and state retention are being applied in many programs on “legacy” nodes.
Another graph from IBS shows that the design starts at 45nm and below will continue to grow at a healthy pace. The data also shows that nodes from 65nm and larger will continue to comprise a strong majority of the overall starts.
Figure 2. IBS: Design starts per process node
TSMC made a comprehensive announcement in September related to “wearables” and the Internet of Things. From their press release:
TSMC’s ultra-low power process lineup expands from the existing 0.18-micron extremely low leakage (0.18eLL) and 90-nanometer ultra low leakage (90uLL) nodes, and 16-nanometer FinFET technology, to new offerings of 55-nanometer ultra-low power (55ULP), 40ULP and 28ULP, which support processing speeds of up to 1.2GHz. The wide spectrum of ultra-low power processes from 0.18-micron to 16-nanometer FinFET is ideally suited for a variety of smart and power-efficient applications in the IoT and wearable device markets. Radio frequency and embedded Flash memory capabilities are also available in 0.18um to 40nm ultra-low power technologies, enabling system level integration for smaller form factors as well as facilitating wireless connections among IoT products.
Compared with their previous low-power generations, TSMC’s ultra-low power processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption and enable significant increases in battery life—by 2X to 10X—when much smaller batteries are demanded in IoT/wearable applications.
The focus on power is quite evident and this means that all of the power management and reduction techniques used in advanced node designs will be coming to legacy nodes soon.
Integration and miniaturization are being pursued from the system-level in, as well as from the process side. Techniques for power reduction and system energy efficiency are central to innovations under way. For mixed-signal program teams, this means there is an added dimension of complexity in the verification task. If this dimension is not methodologically addressed, the level of risk adds a new dimension as well.
Reason 3: Trends are pushing the limits of established design practices
Risk is the bane of every engineer, but without risk there is no progress. And, sometimes the amount of risk is not something that can be controlled. Figure 3 shows some of the forces at work that cause design teams to undertake more risk than they would ideally like. With price and form factor as primary value elements in many growing markets, integration of analog front-end (AFE) with digital processing is becoming commonplace.
Figure 3. Trends pushing mixed-signal out of equilibrium
The move to the sweet spot of manufacturing at 28nm enables more integration, while providing excellent power and performance parameters with the best cost per transistor. Variation becomes great and harder to control. For analog design, this means more digital assistance for calibration and compensation. For greatest flexibility and resiliency, many will opt for embedding a microcontroller to perform the analog control functions in software. Finally, the first wave of leaders have already crossed the methodology bridge into true mixed-signal design and verification; those who do not follow are destined to fall farther behind.
Reason 4: The tipping point accelerants are catching fire
The factors cited in Reason 3 all have a technical grounding that serves to create pain in the chip-development process. The more factors that are present, the harder it is to ignore the pain and get the treatment relief afforded by adopting known best practices for truly mixed-signal design (versus divide and conquer along analog and digital lines design).
In the past design performance was measured in MHz with simple static timing and power analysis. Design flows were conveniently partitioned, literally and figuratively, along analog and digital boundaries. Today, however, there are gigahertz digital signals that interact at the package and board level in analog-like ways. New, dynamic power analysis methods enabled by advanced library characterization must be melded into new design flows. These flows comprehend the growing amount of feedback between analog and digital functions that are becoming so interlocked as to be inseparable. This interlock necessitates design flows that include metrics-driven and software-driven testbenches, cross fabric analysis, electrically aware design, and database interoperability across analog and digital design environments.
Figure 4. Tipping point indicators
Energy efficiency is a universal driver at this point. Be it cost of ownership in the data center or battery life in a cell phone or wearable device, using less power creates more value in end products. However, layering multiple energy management and optimization techniques on top of complex mixed-signal designs adds yet more complexity demanding adoption of “modern” mixed-signal design practices.
Reason 5: Convergence of analog and digital design
Divide and conquer is always a powerful tool for complexity management. However, as the number of interactions across the divide increase, the sub-optimality of those frontiers becomes more evident. Convergence is the name of the game. Just as analog and digital elements of chips are converging, so will the industry practices associated with dealing with the converged world.
Figure 5. Convergence drivers
Truly mixed-signal design is a discipline that unites the analog and digital domains. That means that there is a common/shared data set (versus forcing a single cockpit or user model on everyone).
In verification the modern saying is “start with the end in mind”. That means creating a formal approach to the plan of what will be test, how it will be tested, and metrics for success of the tests. Organizing the mechanics of testbench development using the Unified Verification Methodology (UVM) has proven benefits. The mixed-signal elements of SoC verification are not exempted from those benefits.
Competition is growing more fierce in the world for semiconductor design teams. Not being equipped with the best-known practices creates a competitive deficit that is hard to overcome with just hard work. As the landscape of IC content drives to a more energy-efficient mixed-signal nature, the mounting risk posed by old methodologies may cause causalities in the coming year. Better to move forward with haste and create a position of strength from which differentiation and excellence in execution can be forged.
Summary
2015 is going to be a banner year for mixed-signal design and verification methodologies. Those that have forged ahead are in a position of execution advantage. Those that have not will be scrambling to catch up, but with the benefits of following a path that has been proven by many market leaders.
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In every new version of SOLIDWORKS there is always some new features that steal all of the attention. In this post i will highlight five favorable features in SOLIDWORKS that may not be as known, but still can help you
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Five Stages of Evolving Beta-Cell Dysfunction During Progression to Diabetes
Gordon C. Weir
Dec 1, 2004; 53:S16-S21
Section I: Insulin Resistance-Beta-Cell Connection in Type 2 Diabetes
